In the prior art, integrated circuit memory devices have been developed which store data for indefinite periods of time in the absence of electrical power being applied thereto and which also have the capability of selectively changing or programming the data stored therein. Of particular interest herein is a nonvolatile memory cell which utilizes a floating gate as the nonvolatile element. See, e.g., U.S. Pat. No. 4,314,265 which discloses a four polysilicon layer, floating gate nonvolatile memory cell, and U.S. Pat. No. 4,274,012 which discloses a three polysilicon layer, floating gate nonvolatile memory cell with substrate coupling. Either of these nonvolatile memory cells may be arranged, as is known in the art, to construct nonvolatile random access memories (NOVRAM's) and electrically erasable programmable read only memories (EEPROM's). See, e.g., U.S. Pat. No. 4,300,212, which discloses a NOVRAM device and U.S. Pat. No. 4,486,769, which discloses an EEPROM device.
In U.S. Pat. No. 4,274,012, for example, the disclosed nonvolatile memory cell has three layers of polysilicon, each layer being generally electrically isolated from the substrate and each other by silicon dioxide layers. The first polysilicon layer is a programming electrode. The second polysilicon layer is the floating gate. The floating gate has a portion capacitively coupled to the programming electrode to form a programming tunneling element in which electrons tunnel from the programming electrode to the floating gate. Another portion of the floating gate is capacitively coupled to a n-implant region in the p-type substrate. The n-implant region is a bias electrode. The third polysilicon layer, which is an erase/store electrode, is capacitively coupled to a portion of the floating gate to form an erase tunneling element in which electrons tunnel from the floating gate to the erase/store electrode. Another portion of the erase/store electrode is capacitively coupled to the bias electrode in the substrate.
To initiate tunneling, a high potential, such as 25 volts, is applied to the erase/store electrode while the programming electrode is held at a low potential, such as ground. The substrate bias electrode is caused to be held either at the low potential of the programming electrode or held at the high potential of the erase/store electrode, depending on whether electrons are to be tunneled from or to the floating gate, respectively. With the bias electrode held at the high potential, since the floating gate is being strongly capacitively coupled to the bias electrode, it is elevated to the high potential. Therefore, high potential exists across the programming tunneling element between the programming electrode and the floating gate so that electrons are tunneled onto the floating gate. Conversely, with the bias electrode held at the low potential, the floating gate will also be at the low potential because of the strong capacitive coupling to the bias electrode. Therefore, high potential exists across the erase tunneling element between the floating gate and the erase/store electrode. Electrons will then tunnel from the floating gate to the erase/store electrode. An article which describes electron tunneling structures and operation in greater detail is entitled "Electron Tunneling in Non-Planar Floating Gate Memory Structures", R. K. Ellis, et al., published in the 1982 International Electron Devices Meeting (IEDM) Technical Digest, pages 749-756.
A serious drawback of prior art nonvolatile memory cells as described above is that they do not easily scale to smaller and smaller sizes. There is an ongoing desire to increase the number of memory cells that can be fabricated on an individual chip so as to increase memory density and/or chip yield per wafer. However, the simple miniaturization of the nonvolatile memory cell does not allow the necessary capacitive values and relationships to be maintained for an operational memory device. Furthermore, the overhead requirements of a separate and distinct bias electrode region for a write operation, and floating gate channel region for a read operation, combined with inherent tolerance requirements needed to prevent disturb conditions in memory cells adjacent to the cell whose state is being changed, makes it impractical to shrink such prior art nonvolatile memory cells sufficiently for very high density applications.
A nonvolatile memory which improves on the above described semiconductor memory cells is described in U.S. Pat. No. 4,599,706 to Guterman. This latter memory cell reduces the number of capacitive couplings in the memory cell, since it contained fewer elements, thereby improving device operation. This is because such capacitive couplings introduce losses in obtaining the voltage relationships necessary to induce tunneling of electrons between the polysilicon layers.
Furthermore, device operation and cell dimensions are optimized in this improved memory cell due to its reduced component count and the reduced number of cycles required for a write operation. For example, in an EEPROM version of this improved memory cell, a write cycle that programs the floating gate can be completed in a single cycle. Prior art EEPROM's required an unconditional erase prior to each write cycle.
The nonvolatile memory cell disclosed in U.S. Pat. No. 4,599,706 includes three electrically isolated polysilicon layers, generally as described hereinabove. That is, the first layer forms the programming electrode, the second layer forms the floating gate, and the third layer forms the erase/store electrode. More specifically, a first portion of the second layer is capacitively coupled to the first layer to form a first tunneling element therebetween, and a second portion of the second layer is capacitively coupled to a substrate region of opposite conductivity to the substrate. A third polysilicon layer is capacitively coupled to the second layer to form a second tunneling element. In operation, a reference potential is applied to the first layer. A voltage representative of the data state to be stored by the charge on the second layer is applied to another substrate region of opposite conductivity to the substrate type. The third layer forms the gate of an enhancement mode transistor between each substrate region. Upon application of a selected potential to the third layer, the transistor is turned on to create a conductive path between each substrate region. If the data state voltage is similar to the potential applied to the third layer, electrons will tunnel from the first layer to the second layer leaving the second layer with a net negative charge. Conversely, if the data state voltage is significantly less than the voltage of the potential applied to the third layer, electrons will tunnel from the second layer to the third layer leaving the second layer with a net positive charge.
Thus, an advantage of the device disclosed in U.S. Pat. No. 4,599,706 over prior art devices is that it eliminates the need for capacitive coupling between the third polysilicon layer, the erase/store electrode, and the bias electrode. The transistor switch needed to control the potential of the bias electrode in the nonvolatile cell of the NOVRAM device is also eliminated.
Other limitations still exist with regard to using a three layer polysilicon memory cell as taught in U.S. Pat. No. 4,599,706. The need for three layers of polysilicon results in a surface topology in the resultant memory that has a number of large steps, creating a coverage problem in later processing. Furthermore, the step height cannot be greater than the depth of focus of the apparatus used for forming the memory cell and this is a limitation on the degree of the step height. Scalability is also limited by a polysilicon stringer phenomenon which occurs especially when there are large step heights in the cell being formed. The poly stringer is that portion of the polysilicon layer that is not removed easily during anisotropic etching without over etching. This also puts limitations on the size of the cell.
Furthermore, the need for forming additional silicon dioxide layers in the cell after a given polysilicon layer has been formed creates encroachment of the oxide into the region of the silicon dioxide layer which defines the tunneling element between two layers of polysilicon. Each time a new silicon dioxide layer is formed, the reoxide encroachment of exposed silicon dioxide will become more severe. This reoxide encroachment causes the gap between the two layers of polysilicon to increase, thereby changing the tunneling characteristics across this gap. Since the overlap between polysilicon tunneling elements dictates the minimum cell size, the cell size is limited by this phenomenon. Thus, a three layer polysilicon cell requires more overlap of adjacent layers than a two layer cell because of the greater number of silicon dioxide layers that must be formed in creating the three polysilicon layer structure, and thus the greater reoxide encroachment degradation of the overlapping tunneling element between the first and second polysilicon layers.
In addition, since the operation of a cell is based on specific coupling capacitance ratios defined in the cell, the size of these capacitances also places constraints on the size of the cell. This is because, in order to make the memory cell work, the proportionalities between the capacitances must remain constant. That is, the relationship between the capacitances determines the tunneling coupling which in turn determines the program/erase window of the memory cell. The program/erase window is defined to be the difference between the positive potential on the floating gate when the floating gate has been erased and the level of negative potential on the floating gate when the floating gate has been programmed. The result is an endurance curve which tends to degrade as the number of programming cycles experienced by the floating gate increases. Therefore, if one capacitance value is increased, the others must be changed accordingly. Since a larger coupling capacitance value results from a greater amount of polysilicon layer overlap, the above-described need to maintain a certain minimum amount of layer overlap in order to protect against reoxide encroachment degradation results in the three layer polysilicon cell topology also being less easy to scale down in size due to this interdependence of cell capacitances.
Furthermore, there is little flexibility in the selection of silicon dioxide thickness between adjacent polysilicon layers in the above mentioned three layer polysilicon cell because of reliability problems in the operation of the tunneling mechanism for reduced thickness. Further, since the oxide layer under the floating gate layer is grown at the same time as the tunneling oxide layer between the first polysilicon layer and the floating gate layer in the three layer polysilicon cell, the silicon dioxide thickness of the oxide layer under the floating gate cannot be reduced arbitrarily in order to improve the coupling from the substrate channel to the floating gate. As cell dimensions are reduced laterally without scaling these oxide thicknesses, then the program/erase window also gets smaller and smaller. The capacitive coupling limitations also necessitate higher voltages than would otherwise be necessary. Therefore, it becomes more valuable as the cell is scaled down in size to separate the coupling oxide thickness from being dependent on tunneling oxide thickness. That is, it is advantageous to have a thin coupling oxide and a thick tunneling oxide to create the highest capacitive coupling ratios and thus the lowest possible operating voltage.
It is also important that the memory cell not be alignment sensitive. A difficulty with three layer polysilicon cells is that there are more critical alignment processing steps than would be required in a two layer cell and the silicon dioxide tunneling elements in the programming and erase sides of the floating gate are formed at different times. Since these regions are not matched, the program/erase window is reduced in size, and consequently the cell lifetime is reduced.